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In this work, the electrical isolation of nanowires fabricated on bulk wafers is investigated. It is shown that electrical isolation can be realized with a Ground Plane isolation implant at the beginning of the process flow. For transistors using extensions, it is seen that a relatively high dose of Ground Plane doping is needed in order to avoid punchthrough through a parasitic channel less controlled...
We simulated the static behavior of scaled FinFETs employing a self-consistent Multi-Subband Ensemble Monte Carlo simulator for non-planar devices. To be able to take into account the three-dimensional device structure, the 2D Schrödinger equation is solved in several cross sections; the coupled solution of the 3D Poisson equation and the 1D Boltzmann transport equation through the ensemble Monte...
This work investigates, in detail, the electrically gate-all-around (eGAA) Hexagonal NW FET (HexFET) which combines the high current drive of FinFETs with the excellent electrostatic robustness of conventional Gate-All-Around Nanowire (GAA NW) FETs. We evaluate HexFET as a potential successor to FinFET for 5nm node logic and SRAM applications using first principles atomistic-based modeling, calibrated...
Cathode related current collapse effect in GaN on Si SBDs (Schottky Barrier Diode) is investigated in this paper. Capacitance and current relaxation measurements on diodes and gated-VDP (Van Der Pauw) are associated with temperature dependent dynamic Ron transients analysis showing that the main part of the current collapse at the cathode comes from a combination of electron trapping in the passivation...
This work investigates experimentally the non-linearities of FDSOI MOSFETs from DC to RF frequencies. The effect of the back-gate bias on non-linearity of the device is studied by means of 2nd and 3rd harmonic distortions (HD2 and HD3) extracted from dc I-V curves as well as from large-signal RF measurements using 1-dB and IP3 points. It is shown that the non-linearity is reduced by applying a positive...
Amorphous InGaZnO (a-IGZO) is a candidate material for thin-film transistors (TFTs) owing to its large electron mobility. The development of high functionality circuits requires accurate and efficient circuit simulation that, in turn, is based on compact physical a-IGZO TFTs models. Here we propose a compact physical-based and analytical model of the drain current of a-IGZO TFTs. The model accounts...
Half SRAM cells with strained Si nanowire complementary Tunnel-FETs (CTFET) have been fabricated to explore the capability of TFETs for 6T-SRAM. Static measurements on cells with outward faced n-TFET access transistors have been performed to determine the SRAM butterfly curves, allowing the assessment of cell functionality and stability. The forward p-i-n leakage at certain bias configuration of the...
This work proposes a new method for the extraction of the flatband voltage, effective nanowire width and doping concentration of junctionless nanowire transistors. The accurate extraction of such parameters is essential for the understating of the device behavior and for the prediction of its performance in circuits through analytical models. The method is validated using 3D numerical simulations...
In this paper, we study the impact of different device architectures and material properties on the performance of two-dimensional tunnel FETs (2D TFETs). We show that single-gate (SG) device architecture in case of monolayer and few layers two-dimensional materials perform better than doublegate (DG) architecture. Due to sharper band bending at the tunneling junction, SG device offers shorter tunneling...
An analysis of research in quantum nanoelectronics and nanomagnetics for beyond CMOS devices is presented. Some device proposals and demonstrations are reviewed. Based on that, trends in this field are identified. Principles for development of competitive computing technologies are formulated. Results of beyond-CMOS circuit benchmarking are reviewed.
We report temperature dependent transport properties of back-gated graphene TLM structures in a wide temperature range from 35 K to 450 K. We use gold as the contact material and find that the contact resistance exhibits a strong temperature dependence, dropping considerably to a value of 315±127 Ωμm at 35 K as compared to 957±210 Ωμm at 450 K measured at the Dirac point. This significant drop in...
This study describes the fabrication of hybrid SAM/HfOx gate dielectrics by the radical oxidation in molybdenum disulfide (MoS2)field-effect transistors (FETs). The fabrication process involves the radical oxidation to form HfOx at the surface of metallic HfN, SAM formation by immersion, and deterministic transfer of MoS2 flakes. A subthreshold slope (SS) of 75 mV/dec and small hysteresis were demonstrated...
In this work we demonstrate a semi-empirical GaN HEMT model implemented in Verilog-A format. The model captures accurately the DC operation of test devices fabricated and measured at IMS CHIPS including the thermal effects. In addition, the off-state leakage current is physically modeled as a space-charge limited current prior to the onset of the physical breakdown. The dynamic current recovery of...
We report on a comparison of the ultrathin (sub-10 nm barrier thickness) AlN/GaN heterostructure using two types of buffer layers: 1) carbon doped GaN high electron mobility transistors (HEMTs) and 2) double heterostructure field effect transistor (DHFET). It is observed that the carbon doped HEMT structure shows better electrical characteristics, with a maximum drain current density Id of 1.3 A/mm,...
Low-frequency noise characteristics have been investigated in arrays of 14 nm gate-all-around vertical silicon junction-less nanowire transistors. Extensive measurements have been performed to study the evolution of the 1/f noise as a function of bias for nanowire arrays with different nanowire diameters and several numbers of nanowires in parallel. Measured drain current noise can be explained well...
Channel thickness Tch dependence of electron mobility μκρρ in thin In0.53Ga0.47As channels was investigated at temperatures T from 35 to 300 K using conventional parametric and pulsed ID-measurements, including a novel technique with time resolution down to 10 ns. It is show that accurate mobility measurements can be obtained using low T and/or fast pulsed measurements, thus avoiding significant underestimations...
Based on a novel approach of reading-out cantilever sensors with an exponential response of the measurement signal on adsorption of e.g. molecules, we study cantilever array sensors that enable the detection and discrimination of various different adsorbates. Different cantilever geometries and different ratios of functionalized and unfunctionalized areas on the cantilevers are used together with...
Silicon Carbide (SiC) bipolar integrated circuits are a promising technology for extreme environment applications. SiC bipolar technology shows stable operation over a wide range of temperature. However, the current gain of the devices is suffering from high surface recombination, due to poor oxide passivation. In this paper we propose a gated base structure that offers improved current gain control...
In this paper, a compact model for the gate current in HKMG nMOS transistors is presented. The carrier transport through the multi-stack gate dielectrics of HKMG MOS transistors is shown to be dominated by the Trap Assisted Tunneling and Poole-Frenkel conduction mechanisms. Both these mechanisms occur simultaneously and each is dominant in a particular gate voltage range. The interdependence and simultaneity...
This paper reports the epitaxial-Si growth and dopant diffusion characteristics during fabrication of a vertical thin poly-Si channel (VTPC) transfer gate (TG) structured pixel, which is a possible candidate for future three-dimensional (3D) CMOS image sensor (CIS). Due to the increasing demand for higher resolution sensor, major CIS companies have presented various innovative 3D pixel structures...
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